Si3220/25
In Figure 42, the CID field is zero. As this field is pass through the chain without permutation.
decremented (in LSB to MSB order), the value
decrements for each SDI down the line. The BRDCST,
R/W, and REG/RAM bits remain unchanged as the
control word passes through the entire chain. The odd
SDIs are internal to the device and represent the SDI to
SDI_THRU connection between channels of the same
device. A unique CID is presented to each channel, and
the channel receiving a CID value of zero is the target of
the operation (channel 0 in this case). The last line of
Figure 42 illustrates that in Broadcast mode, all bits
Figures 43 and 44 illustrate WRITE and READ
operations to register addresses via an 8-bit SPI
controller. These operations are performed as a 3-byte
transfer. CS is asserted between each byte, which is
required for CS to be asserted before the first falling
edge of SCLK after the DATA byte to indicate to the
state machine that one byte only should be transferred.
The state of SDI is a “don’t care” during the DATA byte
of a read operation.
SPI Control Word
BRDCST
REG/RAM Reserved
CID[0]
CID[1]
CID[2]
CID[3]
R/W
A
0
0
0
0
B
B
B
B
C
C
C
C
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
SDI0
A
SDI1 (Internal)
SDI2
A
A
SDI3 (Internal)
0
0
A
A
B
B
C
C
0
1
1
0
0
0
0
0
SDI 14
SDI15 (Internal)
1
A
B
C
D
E
F
G
SDI0-15
Figure 42. Sample SPI Control Word to Address Channel 0
CS
SCLK
SDI
CONTROL
ADDRESS
DATA [7:0]
Hi-Z
SDO
Figure 43. Register Write Operation via an 8-Bit SPI Port
CS
SCLK
SDI
CONTROL
ADDRESS
X X X X X X X X
Data [7:0]
SDO
Figure 44. Register Read Operation via an 8-Bit SPI Port
Rev. 1.2
75
SILICON [ SILICON ]
