Si3220/25
3.29. PCM Interface
The Dual ProSLIC devices contain a flexible
programmable interface for the transmission and
reception of digital PCM samples. PCM data transfer is
controlled by the PCLK and FSYNC inputs, PCM Mode
Select, PCM Transmit Start Count (PCMTXHI/
PCMTXLO), and PCM Receive Start Count (PCMRXHI/
PCMRXLO) registers. The interface can be configured
to support from 4 to 128 8-bit timeslots in each frame.
This corresponds to PCLK frequencies of 256 kHz to
8.192 MHz in power-of-2 increments. (768 kHz,
1.536 MHz, and 1.544 MHz are also available for T1
and E1 support.) Timeslots for data transmission and
reception are independently configured with the
PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO.
Special consideration must be given to the PCM
Receive Start Count (PCMRXHI / PCMRXLO) registers.
Changing the PCMRXHI (Reg. 57), PCMRXLO (Reg.
56) on-the-fly while the Si3220/25 is actively passing
audio can cause the digital impedance synthesis block
to perform improperly producing an audible loud white
noise signal across TIP and RING.
To ensure proper device operation, the RX timeslot
registers (PCMRXHI and PCMRXLO, registers 56–57)
should be set during the initialization procedure
immediately after power-up and prior to both enabling
the PCM bus and setting the linefeed to the active state.
The TX timeslot registers (PCMTXHI and PCMTXLO,
registers 54–55) may be changed at any time to
establish audio connections on the PCM bus.
Setting the correct starting point of the data configures
the part to support long FSYNC and short FSYNC
variants, IDL2 8-bit, 10-bit, and B1 and B2 channel time
PCLK
slots. DTX data is high-impedance except for the
duration of the 8-bit PCM transmit. DTX returns to high-
impedance on the negative edge of PCLK during the
LSB or on the positive edge of PCLK following the LSB.
This is based on the setting of the PCMTRI bit of the
PCM Mode Select register. Tristating on the negative
edge allows the transmission of data by multiple
sources in adjacent timeslots without the risk of driver
contention. In addition to 8-bit data modes, a 16-bit
mode is provided for testing. This mode can be
activated via the PCMF bits of the PCM Mode Select
register.
Setting
the
PCMTXHI/PCMTXLO
or
PCMRXHI/PCMRXLO register greater than the number
of PCLK cycles in a sample period stops data
transmission because neither PCMTXHI/PCMTXLO nor
PCMRXHI/PCMRXLO equal the PCLK count. Figures
to adapt to common PCM standards.
As shown in the application schematics in Figures 12
and 13, a pulldown resistor is required on the DTX pin.
A pullup resistor is not allowed on the DTX pin.
Additionally, the PCLK frequency should be chosen
such that there is at least one empty timeslot (hi-Z
timeslot) per 8 kHz frame. If a PCLK is chosen such that
DTX has valid data during the entire frame, choose the
next higher valid PCLK frequency to ensure one or
more empty timeslots in each frame. If an application
requires heavy capacitive loading on the DTX pin, or
more than eight Si322x devices connected to the same
PCM bus, consult your local Silicon Laboratories sales
representative to determine what value of pulldown
resistor should be used.
FSYNC
PCLK_CNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB
LSB
DTX
HI-Z
MSB
LSB
HI-Z
Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS
=
1)
78
Rev. 1.2
SILABS [ SILICON LABORATORIES ]
