Si5013
traditional methods, and it eliminates performance
degradation caused by external component aging. In
4. Functional Description
The Si5013 integrates a high-speed limiting amplifier addition, because external loop filter components are
with a multi-rate CDR unit. No external reference clock not required, sensitive noise entry points are eliminated,
is required for clock and data recovery. The limiting thus making the DSPLL less susceptible to board-level
amplifier magnifies very low-level input data signals so noise sources and making SONET/SDH jitter
that accurate clock and data recovery can be compliance easier to attain in the application.
performed. The CDR uses Silicon Laboratories DSPLL®
4.3. Multi-Rate Operation
technology to recover a clock synchronous to the input
data stream. The recovered clock retimes the incoming The Si5013 supports clock and data recovery for OC-
data, and both are output synchronously via current- 12/3 and STM-4/1 data streams.
mode logic (CML) drivers. Silicon Laboratories’ DSPLL
Multi-rate operation is achieved by configuring the
technology ensures superior jitter performance while
device to divide down the output of the VCO to the
eliminating the need for external loop filter components
desired data rate. The divide factor is configured by the
found in traditional phase-locked loop (PLL)
RATESEL pin. The RATESEL configuration and
associated data rates are given in Table 7.
implementations.
The limiting amplifier includes a control input for
Table 7. Multi-Rate Configuration
RATESEL SONET/SDH
adjusting the data slicing level and provides a loss-of-
signal level alarm output. The CDR includes a bit error
rate performance monitor which signals a high bit error
rate condition (associated with excessive incoming
jitter) relative to an externally adjustable bit error rate
threshold.
1
0
622.08 Mbps
155.52 Mbps
The optional reference clock minimizes the CDR
acquisition time and provides a stable reference for
maintaining the output clock when locking to a reference
is desired.
4.4. Operation Without an External Refer-
ence
The Si5013 can perform clock and data recovery
without an external reference clock. Tying the
REFCLK+ input to VDD and the REFCLK– input to
GND configures the device to operate without an
external reference clock. Clock recovery is achieved by
monitoring the timing quality of the incoming data
relative to the VCO frequency. Lock is maintained by
continuously monitoring the incoming data timing quality
and adjusting the VCO accordingly. Details of the lock
detection and the lock-to-reference functions while in
this mode are described in their respective sections
below.
4.1. Limiting Amplifier
The limiting amplifier accepts the low-level signal output
from a transimpedance amplifier (TIA). The low-level
signal is amplified to a usable level for the CDR unit. The
minimum input swing requirement is specified in Table 2
on page 7. Larger input amplitudes (up to the maximum
input swing specified in Table 2) are accommodated
without degradation of performance. The limiting
amplifier ensures optimal data slicing by using a digital
dc offset cancellation technique to remove any dc bias
introduced by the amplification stage.
Note: Without an external reference the acquisition of data is
dependent solely on the data itself and typically
requires more time to acquire lock than when a refer-
ence is applied.
®
4.2. DSPLL
The Si5013 PLL structure (shown in the "1.Detailed
Block Diagram" on page 4) utilizes Silicon Laboratories'
DSPLL technology to maintain superior jitter
performance while eliminating the need for external loop
4.5. Operation With an External Reference
The Si5013 can also perform clock and data recovery
with an external reference. The device’s optional
external reference clock centers the DSPLL, minimizes
the acquisition time, and maintains a stable output clock
(CLKOUT) when lock-to-reference (LTR) is asserted.
filter
components
found
in
traditional
PLL
implementations. This is achieved using a digital signal
processing (DSP) algorithm to replace the loop filter
commonly found in analog PLL designs. This algorithm
processes the phase detector error term and generates
a digital control value to adjust the frequency of the
voltage-controlled oscillator (VCO). This technology
enables CDR with far less jitter than is generated using
When the reference clock is present, the Si5013 uses
the reference clock to center the VCO output frequency
so that clock and data is recovered from the input data
stream. The device self configures for operation with
one of three reference clock frequencies. This
12
Rev. 1.5
SILICON [ SILICON ]
