Si5013
Table 3. AC Characteristics (Clock and Data)
(V
DD
= 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter
Output Clock Rate
Output Rise Time—OC-12
Output Fall Time—OC-12
Output Clock Duty Cycle—
OC-12/3
Clock to Data Delay
OC-12
OC-3
Clock to Data Delay
OC-12
OC-3
Input Return Loss
Slicing Level Offset
(relative to the internally set
input common mode voltage)
Loss-of-Signal Range
*
(peak-to-peak differential)
Loss-of-Signal Response Time
Symbol
f
CLK
t
R
t
F
Test Condition
Rate Sel = 1
Rate Sel = 0
Min
616
154
—
—
47
Typ
—
—
125
125
50
Max
675
158
155
155
53
Unit
MHz
ps
ps
% of
UI
ps
t
Cr-D
800
4000
0
800
100 kHz–622 MHz
–15
SLICE_LVL = 750 mV to 2.25 V
35
850
—
70
1000
—
ps
dB
860
4100
940
4200
t
Cf-D
V
SLICE
See Figure 8 on page 14.
V
LOS
t
LOS
LOS_LVL = 1.50 to 2.50 V
0
8
—
20
40
25
mV
µs
*Note:
Adjustment voltage is calculated as follows:
V
LOS
= (LOS_LVL – 1.50)/25.
8
Rev. 1.5
SILABS [ SILICON LABORATORIES ]
