Si52147
PCI-E
XPRESS
G
EN
1, G
EN
2, & G
EN
3 N
IN E
O
UTPUT
C
L O C K
G
ENERATOR
Features
PCI-Express Gen 1, Gen 2, &
Gen 3 compliant
Low power push-pull type
differential output buffers
Integrated resistors on differential
clocks
Output enable pin for all clocks
Hardware selectable spread
control
Nine PCI-Express clocks
25 MHz crystal input or clock
input
I
2
C support with readback
capabilities
Triangular spread spectrum
profile for maximum
electromagnetic interference
(EMI) reduction
Industrial temperature:
–40 to 85
o
C
3.3 V power supply
48-pin QFN package
Ordering Information:
See page 20.
Applications
Network attached storage
Multi-function printer
Pin Assignments
Wireless access point
Routers
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
49
GND
VDD
OE0
1
OE1
1
VSS_PCI
VSS_CORE
CKPWRGD_PDB
1
VDD_CORE
SDATA
38
48
47
46
45
44
43
42
41
XOUT
XIN
NC
NC
NC
NC
40
39
37
36
35
34
33
32
31
30
29
28
27
26
DIFF8
DIFF8
VDD
DIFF7
DIFF7
DIFF6
DIFF6
VDD
DIFF5
DIFF5
DIFF4
Description
The Si52147 is a spread-controlled PCIe clock generator that can source
nine PCIe clocks simultaneously. The device has six hardware output
enable control inputs for enabling the respective differential outputs on the
fly while powered on along with the hardware spread control for EMI
reduction.
SSON
2
VSS_PLL3
VSS_PLL4
OE2
1
OE3
1
OE[4:5]
1
OE[6:8]
1
VDD
SCLK
25 DIFF4
VDD
VDD
VSS
DIFF0
DIFF0
DIFF1
DIFF1
DIFF2
DIFF2
DIFF3
Functional Block Diagram
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
DIFF0
XIN/CLKIN
XOUT
DIFF2
DIFF3
DIFF1
PLL1
(SSC)
Divider
DIFF4
DIFF5
DIFF6
SCLK
SDATA
CKPWRGD/PDB
OE [8:0]
SSON
Control & Memory
DIFF7
Control
RAM
DIFF8
Preliminary Rev. 0.1 12/11
Copyright © 2011 by Silicon Laboratories
DIFF3
VSS
Si52147
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
