Si52147
Table 2. AC Electrical Specifications
Parameter
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
DIFF Duty Cycle
Symbol
L
ACC
T
DC
T
R
/T
F
T
CCJ
T
LTJ
V
IH
V
IL
I
IH
I
IL
T
DC
Condition
Measured at V
DD
/2 differential
Measured at V
DD
/2
Measured between 0.2 V
DD
and
0.8 V
DD
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
Min
—
47
0.5
—
—
2
—
—
–35
45
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
250
53
4.0
250
350
VDD+0.3
0.8
35
—
55
50
Unit
ppm
%
V/ns
ps
ps
V
V
uA
uA
%
ps
Any DIFF Clock Skew from the T
SKEW(win
Earliest Bank to the Latest
dow)
Bank
DIFF Cycle to Cycle Jitter
Output PCIe Gen1 REFCLK
Phase Jitter
Output PCIe Gen2 REFCLK
Phase Jitter
Output PCIe Gen2 REFCLK
Phase Jitter
Output Phase Jitter Impact—
PCIe Gen3
DIFF Long Term Accuracy
DIFF Rising/Falling Slew Rate
Voltage High
Voltage Low
Crossing Point Voltage at
0.7 V Swing
Enable/Disable and Setup
Clock Stabilization from
Power-up
Stopclock Set-up Time
T
STABLE
T
SS
T
CCJ
RMS
GEN1
Measured at 0 V differential
Includes PLL BW 1.5–22 MHz,
ζ
= 0.54, Td=10 ns,
Ftrk=1.5 MHz with BER = 1E-12
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB,
ζ
= 0.54, Td=12 ns,
Low Band, F < 1.5 MHz
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB,
ζ
= 0.54, Td=12 ns,
High Band,1.5 MHz < F < Nyquist
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
Measured at 0 V differential
Measured differentially from
±150 mV
—
0
35
40
50
108
ps
ps
RMS
GEN2
0
2
3.0
ps
RMS
GEN2
0
2
3.1
ps
RMS
GEN3
L
ACC
T
R
/T
F
V
HIGH
V
LOW
V
OX
0
—
1
—
–0.3
300
0.5
—
—
—
—
—
1.0
100
8
1.15
—
550
ps
ppm
V/ns
V
V
mV
—
10.0
—
—
1.8
—
ms
ns
Preliminary Rev. 0.1
5
SILABS [ SILICON LABORATORIES ]
