Si5310
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V
DD
= 2.5 V ±5%, T
A
= –40 to 85 °C)
Parameter
Jitter Transfer Bandwidth
(MULTSEL = 1,
MULTOUT = 150 to 167 MHz)*
Symbol
J
BW
Test Condition
Clock Input (MHz) =
9.375 to 10.438
Clock Input (MHz) =
18.750 to 20.875
Clock Input (MHz) =
37.500 to 41.750
Clock Input (MHz) =
75.000 to 83.500
Clock Input (MHz) =
150.000 to 167.000
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.45
40
450
Typ
19
38
75
150
300
0.12
0.06
0.03
0.02
0.01
0.12
0.06
0.03
0.02
0.01
1.5
60
600
Max
26
53
105
210
420
0.4
0.2
0.1
0.066
0.033
0.4
0.2
0.1
0.066
0.033
1.7
150
750
Unit
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ms
µs
ppm
Jitter Transfer Peaking
(MULTSEL = 0,
MULTOUT = 600 to 668 MHz)*
J
P
Clock Input (MHz) =
37.500 to 41.750
Clock Input (MHz) =
75.000 to 83.500
Clock Input (MHz) =
150.000 to 167.000
Clock Input (MHz) =
300.000 to 334.000
Clock Input (MHz) =
600.000 to 668.000
Jitter Transfer Peaking
(MULTSEL = 1,
MULTOUT = 150 to 167 MHz)*
J
P
Clock Input (MHz) =
9.375 to 10.438
Clock Input (MHz) =
18.750 to 20.875
Clock Input (MHz) =
37.500 to 41.750
Clock Input (MHz) =
75.000 to 83.500
Clock Input (MHz) =
150.000 to 167.000
Acquisition Time
T
AQ
After falling edge of
PWRDN/CAL
From the return of valid
CLKIN
Frequency Difference at which PLL goes
out of Lock (REFCLK compared to the
divided down VCO clock)
Frequency Difference at which PLL goes
into Lock (REFCLK compared to the
divided down VCO clock)
LOL
LOCK
150
300
450
ppm
*Note:
See PLL Performance section of this document for test descriptions.
Rev. 1.2
9
SILABS [ SILICON LABORATORIES ]
