Si5338
Table 12. Jitter Specifications1,2
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
GbE Random Jitter
(12 kHz–20 MHz)
CLKIN = 25 MHz
All CLKn at 125 MHz
J
—
0.7
1
ps RMS
GBE
3
4
4
GbE Random Jitter
(1.875–20 MHz)
CLKIN = 25 MHz
All CLKn at 125 MHz
R
—
—
0.38
0.7
0.79
1
ps RMS
ps RMS
JGBE
CLKIN = 19.44 MHz
All CLKn at
OC-12 Random Jitter
(12 kHz–5 MHz)
J
OC12
4
155.52 MHz
CLKIN = 25 MHz
All CLKn at 100 MHz
PCI Express 3.0
Random Jitter
(1.5 MHz—50 MHz)
J
J
—
—
—
0.6
0.7
8
1
1
ps RMS
ps RMS
ps pk-pk
PCIERJ1
Spread Spectrum not
3
4
enabled
CLKIN = 25 MHz
PCI Express 3.0
Random Jitter
(12 kHz—20 MHz)
All CLKn at 100 MHz
Spread Spectrum not
PCIERJ2
3
4
enabled
CLKIN = 25 MHz
PCI Express 3.0
Period Jitter
All CLKn at 100 MHz
Spread Spectrum not
15
4
enabled
CLKIN = 25 MHz
PCI Express 3.0
Cycle-Cycle Jitter
All CLKn at 100 MHz
Spread Spectrum not
enabled
—
—
—
13
10
9
30
30
29
ps pk-pk
ps pk-pk
4
5
J
Period Jitter
N = 10,000 cycles
PER
N = 10,000 cycles
Output MultiSynth
operated in integer or
6
J
ps pk
Cycle-Cycle Jitter
CC
5
fractional mode
Output and feedback
MultiSynth in integer or
fractional mode
Random Jitter
(12 kHz–20 MHz)
R
—
0.7
1.5
ps RMS
J
5
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. DJ for PCI and GBE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
6. Measured in accordance with JEDEC standard 65.
7. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
12
Rev. 0.6
SILICON [ SILICON ]
