Si5338
Table 12. Jitter Specifications1,2 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output MultiSynth
—
3
15
10
ps pk-pk
operated in fractional
5
mode
D
Deterministic Jitter
J
Output MultiSynth
operated in integer
—
2
ps pk-pk
5
mode
Output MultiSynth
—
—
13
12
36
20
ps pk-pk
ps pk-pk
operated in fractional
5
mode
T = D +14xR
J
(See Note )
Total Jitter
(12 kHz–20 MHz)
J
J
7
Output MultiSynth
operated in integer
5
mode
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. DJ for PCI and GBE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
6. Measured in accordance with JEDEC standard 65.
7. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
Table 13. Typical Phase Noise Performance
Offset Frequency
25MHz XTAL
to 156.25 MHz
27 MHz Ref In
to 148.3517 MHz
19.44 MHz Ref In
to 155.52 MHz
Units
100 Hz
1 kHz
–90
–87
–110
–116
–123
–128
–128
–145
–120
–126
–132
–132
–145
–117
–123
–130
–132
–145
10 kHz
100 kHz
1 MHz
10 MHz
dBc/Hz
Rev. 0.6
13
SILICON [ SILICON ]
