Si5338
Synthesis of the output clocks is performed in two The second stage of synthesis consists of the output
stages, as shown in Figure 5. The first stage consists of MultiSynth dividers (M ). Based on a fractional N
x
a high-frequency analog phase-locked loop (PLL) that divider, the MultiSynth divider shown in Figure 6
multiplies the input stage to a frequency within the switches seamlessly between the two closest integer
range of 2.2 to 2.84 GHz. Multiplication of the input divider values to produce the exact output clock
frequency is accomplished using a proprietary and frequency with 0 ppm error.
highly precise MultiSynth feedback divider (N), which
allows the PLL to generate any frequency within its
MultiSynth block calculates the relative phase difference
VCO range with much less jitter than typical fractional N
To eliminate phase error generated by this process, the
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
PLL.
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
Synthesis
Stage 2
Synthesis
Stage 1
(APLL)
MultiSynth
This architecture allows the output of each MultiSynth to
÷M0
produce any frequency from 5 to F /8 MHz. To
2.2-2.84 GHz
VCO
vco
ref
fb
support higher frequency operation, the MultiSynth
divider can be bypassed. In bypass mode, integer divide
ratios of 4 and 6 are supported. This allows for output
Loop
Filter
Phase
Frequency
Detector
MultiSynth
÷M1
frequencies of F /4 and F /6 MHz, which translates
vco
vco
to 367–473.33 MHz and 550–710 MHz respectively.
Because each MultiSynth uses the same VCO output,
there are output frequency limitations when output
MultiSynth
÷M2
MultiSynth
÷N
frequencies greater than F /8 are desired.
vco
MultiSynth
÷M3
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
Figure 5. Synthesis Stages
produce F /4 = 562.5 MHz or F /6 = 375 MHz. Only
vco
vco
two unique frequencies above F /8 can be output:
vco
F
/6 and F /4.
vco
vco
MultiSynth
Fractional-N
Phase
Adjust
Divider
fVCO
fOUT
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
Figure 6. Silicon Labs’ MultiSynth Technology
18
Rev. 0.6
SILICON [ SILICON ]
