S i 5 9 0 / 5 91
1 ps M
AX
J
I T T E R
C
RYSTAL
O
SC ILLA TOR
(XO)
(10 M H
Z TO
525 MH
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 525 MHz
3rd generation DSPLL
®
with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
Si5602
Applications
Ordering Information:
See page 6.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si590/591 is available
with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO,
where a unique crystal is required for each output frequency, the Si590/591
uses one fixed crystal to provide a wide range of output frequencies. This IC
based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis provides
superior supply noise rejection, simplifying the task of generating low jitter
clocks in noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
temperature stability. Specific configurations are factory programmed at time
of shipment, thereby eliminating long lead times associated with custom
oscillators.
Pin Assignments:
See page 5.
(Top View)
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
4
CLK+
Si590 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
2
5
NC
GND
3
4
CLK
Si590 (CMOS)
17 k
*
Any-rate
10–525 MHz
DSPLL
®
Clock
Synthesis
OE
1
6
V
DD
OE
Fixed
Frequency
XO
NC
2
5
CLK–
17 k
*
GND
3
4
CLK+
Si591 (LVDS/LVPECL/CML)
GND
*Note: Output Enable High/Low Options Available – See Ordering Information
Preliminary Rev. 0.25 7/09
Copyright © 2009 by Silicon Laboratories
Si590/591
SILABS [ SILICON LABORATORIES ]
