Si590/591
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
—
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.7
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
V
O
V
OD
mid-level
swing
(diff)
—
0.70
0.8 x V
DD
V
DD
– 0.75
0.95
—
—
—
2
—
—
1.20
V
DD
V
V
PP
V
CMOS Output Option
3
V
OH
V
OL
—
LVPECL/LVDS/CML
CMOS with C
L
= 15 pF
—
—
45
0.4
350
—
55
ps
ns
%
Rise/Fall time (20/80%)
t
R,
t
F
Symmetry (duty cycle)
SYM
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
Notes:
1.
50
to V
DD
– 2.0 V.
2.
R
term
= 100
(differential).
3.
C
L
= 15 pF. Sinking or sourcing 12 mA for V
DD
= 3.3 V, 6 mA for V
DD
= 2.5 V, 3 mA for V
DD
= 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1
for 50 MHz < F
OUT
< 525 MHz
(LVPECL/LVDS/CML)
Phase Jitter (RMS)
2
for 50 MHz < F
OUT
< 160 MHz
(CMOS)
Symbol
Test Condition
12 kHz to 20 MHz
Min
—
Typ
0.5
Max
1.0
Units
ps
J
J
12 kHz to 20 MHz
—
0.6
1.0
ps
Notes:
1.
Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only.
2.
Single-ended CMOS output phase jitter measured using 33
series termination into 50
phase noise test equipment.
3.3 V supply voltage option only.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
—
—
Max
3
35
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Preliminary Rev. 0.25
3
SILABS [ SILICON LABORATORIES ]
