Si8430/31/35
Table 3. Electrical Characteristics (Continued)
(V
DD1
= 5 V ±10%, V
DD2
= 5 V ±10%, T
A
= –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current
(All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8430Bx, Si8435Bx
V
DD1
V
DD2
Si8431Bx
V
DD1
V
DD2
Timing Characteristics
Si843xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|t
PLH
- t
PHL
|
Propagation Delay Skew
Channel-Channel Skew
Si843xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|t
PLH
- t
PHL
|
Propagation Delay Skew
Channel-Channel Skew
t
PHL
, t
PLH
PWD
t
PSK(P-P)
t
PSK
See Figure 2
See Figure 2
0
—
3.0
—
—
—
—
—
6.0
1.5
2.0
0.5
150
6.0
9.5
2.5
3.0
1.8
Mbps
ns
ns
ns
ns
ns
t
PHL
, t
PLH
PWD
t
PSK(P-P)
t
PSK
See Figure 2
See Figure 2
0
—
—
—
—
—
—
—
—
—
—
—
1.0
250
35
25
40
35
Mbps
ns
ns
ns
ns
ns
—
—
—
—
2.9
14.3
7.0
11.0
4.4
17.9
8.8
13.8
mA
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 85
,
±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4.
Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.5
SILABS [ SILICON LABORATORIES ]
