SiM3C1xx
4.1.5.1. Normal Mode
Normal mode encompasses the typical full-speed operation. The power consumption of the device in this mode will
vary depending on AHB/APB clock speeds and the settings of CLKCTRL and the peripherals.
4.1.5.2. Power Mode 1
Power Mode 1 occurs when the core executes code from RAM instead of Flash. The power consumption of the
device is slightly less than normal mode when in PM1.
4.1.5.3. Power Mode 2
In Power Mode 2, the core halts and the peripherals run at full speed. To place the device in this mode, the clock
settings in CLKCTRL should remain the same as Normal or Power Mode 1 and the core should execute a wait-for-
interrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service routine,
the interrupt that wakes the device from PM2 must be of a sufficient priority to be recognized by the core.
4.1.5.4. Power Mode 3 Fast Wake
Power Mode 3 Fast Wake occurs when all the clocks are stopped except for the LFOSC0 or RTC0OSC. The core
and the peripherals are halted in this mode.
The following sequence places the device in Power Mode 3 Fast Wake:
1. All DMA channels must be disabled by using the global enable/disable DMAEN in the DMA Controller
(DMACTRL0).
2. Firmware should enable PM3 Fast Wake in the PM3CN register and set the core clock to run off of the
LFOSC0 or RTC0OSC to achieve the lowest power.
3. CLKCTRL CONTROL register settings must be modified to set the AHB and APB clocks to the Low Power
Oscillator.
4. Firmware should then execute a WFI or WFE instruction.
If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3FW
must be of a sufficient priority to be recognized by the core.
By keeping the core clock running at a slow frequency in PM3 and changing the AHB and APB clocks to the Low
Power Oscillator, the device can wake up faster than in standard Power Mode 3 at the expense of higher power
consumption.
4.1.5.5. Power Mode 3
Power Mode 3 occurs when all the clocks are stopped, and the core and the peripherals are halted.
The following sequence places the device in Power Mode 3:
1. All DMA channels must be disabled by using the global enable/disable DMAEN in the DMA Controller
(DMACTRL0).
2. Firmware should disable PM3 Fast Wake in the PM3CN register.
3. Firmware should then execute a WFI or WFE instruction.
If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3 must
be of a sufficient priority to be recognized by the core.
4.1.5.6. Power Mode 9
In Power Mode 9, the core and all peripherals are halted, all clocks are stopped, and the pins and peripherals are
set to a lower power mode. In addition, standard RAM contents are not preserved, though retention RAM contents
are still available after exiting the power mode. This mode provides the lowest power consumption for the device,
but requires an appropriate reset to exit. The available reset sources to wake from PM9 are controlled by the
Power Management Unit (PMU).
To enter this mode, firmware must write the SLEEPDEEP bit in the ARM System Control Register. Firmware must
then execute a WFI or WFE instruction. The core will remain in PM9 until an enabled reset source occurs.
Preliminary Rev. 0.8
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SILICON [ SILICON ]
