STK12C68 (SMD5962-94599)
HARDWARE MODE SELECTION
E
H
L
L
X
W
X
H
L
X
HSB
H
H
H
L
A
12
- A
0
(hex)
X
X
X
X
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
MODE
Not Selected
Read SRAM
Write SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
I/O
Output High Z
Output Data
Input Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
POWER
Standby
Active
Active
l
CC2
m
o
NOTES
L
H
H
Active
n, o
l
CC2
L
H
H
Active
n, o
Note m: HSB
STORE
operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the
STORE
(if any) completes, the
part will go into standby mode, inhibiting all operations until HSB rises.
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note o: I/O state assumes G < V
IL
. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE
STORE
CYCLE
SYMBOLS
NO.
Standard
22
23
24
25
26
t
STORE
t
DELAY
t
RECOVER
t
HLHX
t
HLBL
Alternate
t
HLHZ
t
HLQZ
t
HHQX
STORE
Cycle Duration
Time Allowed to Complete SRAM Cycle
Hardware
STORE
High to Inhibit Off
Hardware
STORE
Pulse Width
Hardware
STORE
Low to Store Busy
PARAMETER
(V
CC
= 5.0V
±
10%)
e
STK12C68
UNITS NOTES
MIN
MAX
10
1
700
15
300
ms
μs
ns
ns
ns
i, p
i, q
p, r
Note p: E and G low for output behavior.
Note q: E and G low and W high for output behavior.
Note r: t
RECOVER
is only applicable after t
STORE
is complete.
HARDWARE
STORE
CYCLE
25
t
HLHX
HSB (IN)
24
t
RECOVER
22
t
STORE
HSB (OUT)
26
t
HLBL
HIGH IMPEDANCE
HIGH IMPEDANCE
23
t
DELAY
DQ (DATA OUT)
DATA VALID
DATA VALID
Document Control #ML0008 Rev 0.7
February 2007
6
SIMTEK [ SIMTEK CORPORATION ]
