STK14C88-3
32
VCCX
HSB
1
2
3
4
VCAP
A14
A12
31
30
W
A13
A7
A6
A5
A4
A3
NC
A2
A1
A0
29
28
27
26
25
24
23
22
21
20
19
18
A8
5
6
7
8
A9
A11
G
NC
9
A10
E
10
11
12
DQ7
DQ6
DQ5
DQ4
DQ3
Portagee
Joe
DQ0
DQ1
DQ2
VSS
13
14
32-Pin SOIC
32-Pin PDIP
15
16
17
PIN DESCRIPTIONS
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
14
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
Power Supply
I/O
Power: 3.3V, ± 10%
CCX
HSB
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
V
V
Power Supply
Power Supply
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
CAP
Ground
SS
Rev 0.6
Document Control #ML0015
February 2007
2
SIMTEK [ SIMTEK CORPORATION ]
