STK14C88-3
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ i, j
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
STK14C88-3-
35
MIN
35
25
25
12
0
25
0
0
13
5
MAX
(V
CC
= 3V - 3.6V)
e
STK14C88-3-
45
MIN
45
30
30
15
0
30
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNITS
Note j: W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be
≥
V
IH
during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1:
W Controlled
k, l
12
t
AVAV
ADDRESS
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
14
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
20
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
k, l
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
Document Control #ML0015 Rev 0.6
February 2007
6
SIMTEK [ SIMTEK CORPORATION ]
