STK14C88
SOFTWARE
STORE/RECALL
MODE SELECTION
E
W
A
13
- A
0
(hex)
0E38
31C7
03E0
3C1F
303F
0FC0
0E38
31C7
03E0
3C1F
303F
0C63
MODE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
I/O
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
POWER
NOTES
L
H
Active
r, s, t
l
CC2
L
H
Active
r, s, t
SOFTWARE-CONTROLLED
STORE/RECALL
CYCLE
v
SYMBOLS
NO.
Standard
33
34
35
36
37
t
AVAV
t
AVEL
t
ELEH
t
ELAX
t
RECALL
Alternate
t
RC
t
AS
t
CW
STORE/RECALL
Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
Address Hold Time
RECALL
Duration
PARAMETER
MIN
25
0
20
20
20
MAX
MIN
35
0
25
20
20
STK14C88-25
(V
CC
= 5.0V
±
10%)
e
STK14C88-35
MAX
STK14C88-45
UNITS NOTES
MIN
45
0
30
20
20
MAX
ns
ns
ns
ns
μs
n
u
u
u
Note r:
Note s:
Note t:
Note u:
Note v:
The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
While there are 15 addresses on the STK14C88, only the lower 14 are used to control software modes.
I/O state assumes G < V
IL
. Activation of nonvolatile cycles does not depend on state of G.
The software sequence is clocked with E controlled READs.
The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a
STORE
cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a
RECALL
cycle. W must be high during all six consecutive cycles.
SOFTWARE
STORE/RECALL
CYCLE:
E CONTROLLED
t
AVAV
ADDRESS
34
ADDRESS #1
33
t
AVAV
ADDRESS #6
33
t
AVEL
E
t
ELEH
35
t
ELAX
28
37
/
t
RECALL
36
t
STORE
DQ (DATA
DATA VALID
DATA VALID
HIGH IMPEDANCE
Document Control #ML0014 Rev 0.3
February, 2007
8