STK14EC16
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
t
AXQXd
t
AVAVc
t
AVQVd
SYMBOLS
#1
#2
t
ELQV
t
ELEHc
t
AVQVd
t
GLQV
t
BLQV
t
AXQXd
t
ELQX
t
EHQZe
t
BLQX
t
GLQX
t
GHQZe
t
BHQZe
t
ELICCHb
t
EHICCLb
t
OLZ
t
OHZ
t
OH
t
LZ
t
HZ
Alt.
t
ACS
t
RC
t
AA
t
OE
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Byte Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
Byte Enable to Output Active
Output Enable to Output Active
Output Disable to Output Inactive
Byte Enable to Output Inactive
t
PA
t
PS
Chip Enable to Power Active
Chip Disable to Power Standby
0
15
0
7
7
0
3
3
7
7
0
15
15
10
10
3
3
STK14EC16-15
MIN
MAX
15
25
MIN
Preliminary
STK14EC16-25
MAX
25
STK14EC16-45
MIN
MAX
45
45
UNITS
ns
ns
25
12
12
3
3
10
10
0
10
10
0
25
45
20
20
ns
ns
ns
ns
ns
15
15
ns
ns
ns
15
15
ns
ns
ns
45
ns
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low, LB and UB select bytes read.
Measured
±
200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1:
Address Controlled
c,d,f
t
AVAV
(2)
Address
t
AVQV
Data Output
Previous Data Valid
t
AXQX
(6)
Address Valid
(3)
Output Data Valid
SRAM READ CYCLE #2:
E and G Controlled
ADDR ESS
t
E LE H
1
t
EL Q V
2
29
t
EHAX
11
t
EHI CC L
7
t
EHQ Z
E
27
6
t
ELQ X
G
t
AV QV
4
8
t
G L Q X
t
G L QV
9
t
GH Q Z
3
DQ (D ATA OUT)
10
t
ELI CC H
AC T IVE
DAT A VAL ID
I
CC
ST AND BY
Document Control #ML0061 Rev 1.1
Jan, 2008
6
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
