STK15C88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAV
f
t
AVQV
t
GLQV
t
AXQX
g
t
ELQX
t
EHQZ
h
t
GLQX
t
GHQZ
h
t
ELICCH
e
t
EHICCL
d
e
(V
CC
= 5.0V
±
10%)
STK15C88-25
STK15C88-45
UNITS
MIN
MAX
25
25
25
10
5
5
10
0
10
0
25
0
45
0
15
5
5
15
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f, g
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
DATA VALID
3
t
AVQV
SRAM READ CYCLE #2: E Controlled
f
2
t
AVAV
ADDRESS
6
E
t
ELQX
7
t
EHQZ
1
t
ELQV
11
t
EHICCL
G
4
8
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
STANDBY
t
GLQV
9
t
GHQZ
DATA VALID
I
CC
Document Control #ML0016 Rev 0.3
February, 2007
4
SIMTEK [ SIMTEK CORPORATION ]
