STK16CA8
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
SYMBOLS
#1, #2
t
ELQV
t
AVAVf
t
AVQVg
t
GLQV
t
AXQXg
t
ELQX
t
EHQZ
h
(V
CC
= 3.0V +20%, -10%)
PARAMETER
STK16CA8-25
MIN
MAX
25
25
25
10
3
3
10
0
10
0
25
0
35
0
13
0
45
3
3
13
0
15
35
35
15
3
3
15
STK16CA8-35
MIN
MAX
35
45
45
20
STK16CA8-45
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
e
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
GLQX
t
GHQZh
t
ELICCH
t
EHICCLe
t
PA
t
PS
Note f: W must be high during SRAM READ cycles.
Note g: Device is continuously selected with E and G both low.
Note h: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
2
t
AVAV
ADDRESS
5
3
t
AVQV
DATA VALID
t
AXQX
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
f
2
t
AVAV
ADDRESS
6
1
t
ELQV
1
1
t
EHICCL
7
t
EHQZ
E
t
ELQX
G
8
t
GLQX
DQ (DATA OUT)
t
ELICCH
ACTIVE
t
GLQV
4
9
t
GHQZ
DATA VALID
10
I
CC
STANDBY
September 2003
3
Document Control # ML0023 rev 0.1
SIMTEK [ SIMTEK CORPORATION ]
