STK22C48
PIN CONFIGURATIONS
V
CAP
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(TOP)
V
CCX
W
HSB
A
8
A
9
NC
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28-pin 300 mil SOIC
28-pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name
A
10
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
V
SS
Input
I/O
Input
Input
Input
Power Supply
Power Supply
I/O
Description
Address: The 11 address inputs select one of 2,048 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, ±10%
Ground
Document Control #ML0004 Rev 2.0
Feb, 2008
2
SIMTEK [ SIMTEK CORPORATION ]
