STK22C48
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
1
2
3
4
5
6
7
8
9
10
11
t
ELQV
t
AVAVg,
t
ELEHg
t
AVQVh
t
GLQV
t
AXQXh
t
ELQX
t
EHQZi
t
GLQX
t
GHQZi
t
ELICCHf
t
EHICCLf
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
45
5
5
10
0
15
25
25
10
5
5
15
PARAMETER
MIN
MAX
25
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(V
CC
= 5.0V
±
10%)
e
STK22C48-25
STK22C48-45
UNITS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
g, h
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
DATA VALID
3
t
AVQV
SRAM READ CYCLE #2:
E and G Controlled
g
ADDR ESS
t
E LE H
1
t
EL Q V
2
29
t
EHAX
11
t
EHI CC L
7
t
EHQ Z
E
27
6
t
ELQ X
G
t
AV QV
4
8
t
G L Q X
t
G L QV
9
t
GH Q Z
3
DQ (D ATA OUT)
10
t
ELI CC H
AC T IVE
DAT A VAL ID
I
CC
ST AND BY
Document Control #ML0004 Rev 2.0
Feb, 2008
4
SIMTEK [ SIMTEK CORPORATION ]
