STK22C48
SYMBOLS
NO.
#1
14
15
16
17
18
19
20
21
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ i, j
t
WHQX
#2
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
20
10
0
20
0
0
10
5
MAX
MIN
30
15
0
30
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
STK22C48-25
STK22C48-45
UNITS
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be
≥
V
IH
during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1:
W Controlled
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
Document Control #ML0004 Rev 0.3
February 2007
5
SIMTEK [ SIMTEK CORPORATION ]
