U632H64
Software Controlled STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation)
tcR
tcR
(29)
(29)
ADDRESS 6
ADDRESS 1
Ai
E
th(A)SR
(35)
tw(E)SR
(34)
tw(E)SR
(34)
tdis(E)
(5)
tsu(A)SR
th(A)SR
(33)
(33)
tsu(A)SR
(35)
t
t
d(E)R(32)
d(E)S(31)
DQi
Output
High Impedance
VALID
VALID
tdis(E)SR
(30)
Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)
tcR
(29)
ADDRESS 6
ADDRESS 1
Ai
E
t
h(A)SR (35)
tw(E)SR
(34)
(33)
tsu(A)SR
(33)
tsu(A)SR
th(A)SR
(35)
td(E)R
td(E)S
(31)
(32)
DQi
Output
High Impedance
VALID
VALID
tdis(E)SR
(30)
u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U632H64 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
August 15, 2006
STK Control #ML0047
9
Rev 1.1
SIMTEK [ SIMTEK CORPORATION ]
