+5V
V
CC
PFI
R
2
PFO
V-
GND
5.0 - 1.25 = 1.25 - V
TRIP
R
2
R
1
PFO
+5V
0V
0V
R
1
Buffered RESET connects to System Components
+5V
V
CC
+5V
V
CC
µP
RESET
4.7KΩ
RESET
GND
GND
Figure 16. Interfacing to Microprocessors with
Bidirectional RESET I/O
*V
TRIP
V-
*V
TRIP
is a negative voltage
Figure 15. Monitoring a Negative Voltage
Interfacing to Microprocessors with
Bidirectional Reset Pins
Microprocessors with bidirectional reset pins,
such as the Motorola 68HC11 series, can
contend with this series' RESET output. If, for
example, the RESET output is driven high and
the
µP
wants to pull it low, indeterminate logic
levels may result. To correct this, connect a
4.7KΩ resistor between the RESET output and
the
µP
reset I/O, as in
Figure 16.
Buffer the
RESET output to other system components.
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
13
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