t
WP
t
WD
+5V
t
WD
WDI
WDO
RESET*
0V
+5V
0V
t
WD
+5V
0V
t
RS
+5V
RESET*
0V
* externally triggered LOW by MR,
RESET is for the SP813L/813M only
Figure 14. SP705/706/813L/813M Watchdog Timing Waveforms
Typically, WDO will be connected to the
non-maskable interrupt input (NMI) of a
µP.
When V
CC
drops below the reset threshold,
WDO will go LOW whether or not the watch-
dog timer has timed out. Normally this would
trigger an NMI but RESET goes LOW simulta-
neously, and thus overrides the NMI.
If WDI is left unconnected, WDO can be used as
a low-line output. Since floating WDI disables
the internal timer, WDO goes LOW only when
V
CC
falls below the reset threshold, thus func-
tioning as a low-line output.
+5V
V
CC
V
RT
V
RT
0V
+5V
WDO
0V
t
RS
+5V
t
RS
RESET
0V
+5V
MR*
0V
t
MD
*externally driven LOW
t
MR
Figure 15. SP705/706 Timing Diagrams with WDI Tri-stated. The SP707/708/813L/813M RESET Output is the Inverse
of the RESET Waveform Shown.
SP705DS/09
SP705 Low Power Microprocessor Supervisory Circuits
© Copyright 2000 Sipex Corporation
10
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