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SP706EN 参数 Datasheet PDF下载

SP706EN图片预览
型号: SP706EN
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗微处理器监控电路 [Low Power Microprocessor Supervisory Circuits]
分类和应用: 微处理器监控
文件页数/大小: 18 页 / 200 K
品牌: SIPEX [ SIPEX CORPORATION ]
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PIN DESCRIPTION
NAME
FUNCTION
SP705/706
DIP/
SOIC
µSOIC
SP707/708
DIP/
SOIC
µSOIC
SP813L/813M
DIP/
SOIC
µSOIC
MR
Manual Reset - This input triggers a reset pulse
when pulled below 0.8V. This active-LOW input
has an internal 250
µ
A pull-up current. It can be
driven from a TTL or CMOS logic line or shorted
to ground with a switch
+5V power supply
Ground reference for all signals
Power-Fail Input - When this voltage monitor input
is less than 1.25V, PFO goes LOW. Connect PFI
to ground or V
CC
when not in use.
Power-Fail Output - This output is HIGH until PFI
is less than 1.25V.
Watchdog Input - If this input remains HIGH or
LOW for 1.6s, the internal watchdog timer times
out and WDO goes LOW. Floating WDI or
connecting WDI to a high-impedance tri-state
buffer disables the watchdog feature. The internal
watchdog timer clears whenever RESET is
asserted, WDI is tri-stated, or whenever WDI sees
a rising or falling edge.
No Connect.
Active-LOW RESET Output - This output pulses
LOW for 200ms when triggered and stays LOW
whenever V
CC
is below the reset threshold (4.65V
for the SP705/707/813L and 4.40V for the
SP706/708). It remains LOW for 200ms after V
cc
rises above the reset threshold or MR goes from
LOW to HIGH. A watchdog timeout will not trigger
RESET unless WDO is connected to MR.
Watchdog Output - This output pulls LOW when
the internal watchdog timer finishes its 1.6s count
and does not go HIGH again until the watchdog is
cleared. WDO also goes LOW during low-line
conditions. Whenever V
CC
is below the reset
threshold, WDO stays LOW. However, unlike
RESET, WDO does not have a minimum pulse
width. As soon as V
CC
is above the reset
threshold, WDO goes HIGH with no delay.
Active-HIGH RESET Output - This output is the
complement of RESET. Whenever RESET is
HIGH, RESET is LOW, and vice versa. Note the
SP813L/813M has a reset output only.
1
3
1
3
1
3
V
CC
GND
PFI
2
3
4
4
5
6
2
3
4
4
5
6
2
3
4
4
5
6
PF O
5
7
5
7
5
7
WDI
6
8
-
-
6
8
N.C.
-
-
6
8
-
-
RESET
7
1
7
1
-
-
WD O
8
2
-
-
8
2
RESET
-
-
8
2
7
1
Table 1. Device Pin Description
SP705DS/09
SP705 Low Power Microprocessor Supervisory Circuits
© Copyright 2000 Sipex Corporation
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