ML2726
MODE CONTROL AND INTERFACE LINES
1
XCEN
I (CMOS)
Enables the bandgap reference and
voltage regulators when high. Consumes
only leakage current in STANDBY mode
when low. This is a CMOS input, and the
thresholds are referenced to VDD and
VSS.
XCEN
1
VDD
31
2
RXON
I (CMOS)
TX/RX Control Input. Switches the
transceiver between TRANSMIT and
RECEIVE modes. Circuits are powered
up and signal paths reconfigured
according to the operating mode. This is
a CMOS input, and the thresholds are
referenced to VDD and VSS.
RXON
2
DIN
30
8
VSS
3
PAON
O (CMOS)
PA Control Output. Enables the off-chip
PA at the correct times in a Transmit slot.
Goes high when transmit RF is present
at TXO; goes low
5μs
before transmit RF
is removed from TXO. Has interlock logic
to shut down the PA if the PLL does not
lock.
VDD
31
3
PAON
8
VSS
9
FREF
I
Input for the 9.216MHz, 12.288MHz,
18.432MHz or 25.576MHz reference
frequency. This input is used as the
reference frequency for the PLL and as a
calibration frequency for the on-chip
filters. An AC-coupled sine or square
wave source drives this self-biased input.
VCCA
24
9
FREF
40k
40k
8
VSS
11
QPO
O
Charge Pump Output of the phase
detector. This is connected to the
external PLL loop filter.
RVPLL
10
11 QPO
8
VSS
PRELIMINARY DATASHEET
OCT 2007
10
EDS-105982 REV P01
SIRENZA [ SIRENZA MICRODEVICES ]
