ML2726
SYMBOL
V
RSMD
V
RSMN
V
RSMXC
PARAMETER
RSSI midrange voltage
RSSI minimum voltage
RSSI maximum voltage (clipped)
CONDITIONS
-40dBm into RXI
No signal into RXI
-10dBm into RXI
1.6
MIN
1.4
TYP
1.7
75
1.95
MAX
2.0
UNITS
V
mV
V
TRANSMIT RF MIXER
P
OSE
P
ODIF
Z
OUT
Output power, single ended
Output power, differential
Output impedance
TRXO or TRXOB, f
C
=2.445GHz
P
(TRXO,TRXOB)
, f
C
=2.445GHz
TRXO or TRXOB, f
C
=2.445GHz
-3
-1
1
3
12+j0
5
6
dBm
dBm
Ω
TRANSMIT MODULATION
f
DEV
f
OS
Modulation Deviation, @2.4GHz
Modulation center frequency offset
200us of consecutive ‘1’s or ‘0’s
50us after RXON low
750
-75
768
786
+75
kHz
kHz
TRANSMIT DATA FILTER
BW
TX
Transmit Data Filter Bandwidth
TX spurious
Image
INTERFACE LOGIC LEVELS
INPUTS (DIN, XCEN, RXON, DATA, CLK, EN)
V
IH
V
IL
I
B
C
IN
Input high voltage
Input low voltage
Input bias current
Input capacitance
(measured at 1MHz)
(never exceed VDD)
0.75*VDD
0
-5
0
4
VDD
0.25*VDD
5
V
V
μA
pF
3dB Bandwidth
2.1
-25
-20
MHz
dBc
dBc
OUTPUTS (DOUT, PAON)
V
OH
V
OL
I
o
V
OH
V
OL
I
o
DOUT high voltage
DOUT low voltage
DOUT sink/source current
PAON output high voltage
PAON output low voltage
PAON source/sink current
Sourcing 0.5mA
Sinking 0.5mA
0.5
I
o
=0.1mA
I
o
=-0.1mA
0.1
VDD-0.4
0.4
VDD-0.4
0.4
V
V
mA
V
V
mA
3 WIRE SERIAL BUS TIMING
t
r
t
f
t
ck
t
ew
t
l
t
se
t
s
t
h
CLK input rise time
CLK input fall time
CLK period
CLK pulse width
Delay from last CLK falling edge
EN setup time to ignore next
rising CLK
DATA-to-CLK setup time
DATA-to-CLK hold time
50
100
15
15
15
15
See Figure 4
15
15
ns
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY DATASHEET
OCT 2007
6
EDS-105982 REV P01
SIRENZA [ SIRENZA MICRODEVICES ]
