ST7920
ST7920 Specification Reversion History
Description
Version
Date
1. VCC changed to VDD.
2. VLCD changed from VCC-V5 to V0-VSS.
C1.7
2000/12/15
3. DC characteristics input High voltage (Vih) changed to 0.7VDD.
4. DC characteristics output High voltage (Voh) changed to 0.8VDD.
1. Chip Size changed.
2. ICON 256 dots changed to 240 dots.
3. XOFF normal high sleep Low changed to normal low sleep High.
4. Added XOFF application.
5. Modified application of ST7920: PIN 4~6 are floating. (PIN 4~6 are test pin)
6. Modified voltage doubler CAP1P, CAP1M, CAP2M capacitors polarity
1. Icon RAM TABLE changed. (TABLE-6)
C1.8
C1.9
2001/03/01
2. Booster description modified. (PAGE-29)
2001/05/28 3. AC Characteristics modified.
4. Added 2Line 16 Chinese Word (32Com X 256Seg) application circuit.
5. Added oscillation resistor’s relation to power consumption and frequency.
1. Added Register initial values.
2. Voltage booster CAP1M CAP1P polarity changed (PAGE-30).
C2.0
V2.0
2001/07/03
2001/08/17
1. Modified Table 7 (PAGE-14).
2. Change to English version.
V2.0c
V2.0d
V3.0
V3.1
V3.2
V3.3
V3.4
2001/10/18 1. Modified page-38 Serial interface timing diagram.
2002/05/09 1. Add the standard code (Japan, GB code, BIG-5 code).
2002/10/11 1. Delete sleep mode function.
2003/04/11 1. Modified GDRAM Address (AC5…AC0, 00h…3Fh).
2003/09/09 1. Add the CGROM and HCGROM test application circuit.
2004/03/29 1. Updat the using method for ICON.
2005/5/24 1. ICON no used.
1. Add VOUT voltage limitation.
2005/5/24
V3.5
V3.6
2. Remove IRAM related descriptions.
1. Fix the check sum count number on Page 28~30.
2005/6/6
655360->655362, 10240->10242.
2. Modify the description about serial interface.
V3.7
V3.8
V3.9
2007/7/24 1. Add CGROM/HCGROM checksum operation time.
2007/12/20 1. Add “Clear DDRAM” step before check sum process.
2008/3/3
1. Modify 4-bit initial sequence.
1. Add Font Code “0F” at Page 1.
2. Modify the description of Font Code Table at Page 1.
V4.0
2008/8/18
V4.0
2/49
2008/08/18
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
