Multiple Channel 1°C Temperature Sensors with Beta Compensation
Datasheet
7.3
Status Register
Table 7.3 Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
02h
R
Status
BUSY
-
-
HIGH
LOW
FAULT
THERM
-
00h
The Status Register reports general error conditions. To identify specific channels, refer to
and
The individual Status Register bits are
cleared when the appropriate High Limit, Low Limit, or Therm Limit register has been read or cleared.
Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either
the ALERT or THERM pins to be asserted.
Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit.
See the High Limit Status Register for specific channel information (Section
When set, this bit
will assert the ALERT pin.
Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low
limit. See the Low Limit Status Register for specific channel information (Section
When set, this
bit will assert the ALERT pin.
Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode
channels. See the External Diode Fault Register for specific channel information (Section
When
set, this bit will assert the ALERT pin.
Bit 1 - THERM - This bit is set when the any of the temperature channels exceeds its programmed
Therm Limit. See the Therm Limit Status Register for specific channel information (Section
7.4
Configuration Register
Table 7.4 Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
03h
R/W
09h
Configuration
MASK_
ALL
RUN/
STOP
ALERT/
COMP
RECD1
RECD2
RANGE
DAVG_
DIS
APDD
00h
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.
‘0’ - (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT
pin will be asserted.
‘1’ - - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is
configured in comparator mode. The Status Registers will be updated normally.
Bit 6 - RUN / STOP - Controls Active/Standby modes.
‘0’ (default) - The device is in Active mode and converting on all channels.
‘1’ - The device is in Standby mode and not converting.
Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.
‘0’ (default) - The ALERT pin acts as described in
‘1’ - The ALERT pin acts in comparator mode as described in
In this mode the
MASK_ALL bit is ignored.
Revision 1.41 (02-23-12)
30
SMSC EMC1413 / EMC1414
DATASHEET
SMSC [ SMSC CORPORATION ]
