MANAGEMENT
MAC Access to PHY Management Registers
The interface to these registers is via the MDC and MDIO signals. The address of the LAN83C180 is
specified by the PA<4:0> static inputs. The MD command is issued by the MAC and can be read or write:
START
DATA
01b
01b
OP
CODE
10b
01b
PHY
ADDRESS
5 Bits
5 Bits
REG
NUMBER
5 Bits
5 Bits
COMMAND
READ
WRITE
PREAMBLE
32 Bits of 1
32 Bits of 1
TA
Z0b
10b
DATA
16 bit from
PHY
16 bit from
MAC
RESISTER SET
The following register set is implemented in the LAN83C180 device. Each of the registers is accessible to the MAC
at the specified offset. The bit types in the bit description tables follow the following convention:
SC = Self clear
RO = Read only
RW = Read or write
LL = Latch low until register read
LH = Latch high until register read
Res = Reserved
Reg 0 - Control Register
BIT
15
14
13
12
11
10
9
8
7
6:0
BIT NAME
Reset
Loopback
Speed Selection
ANEG Enable
Power Down
Isolation
Restart ANEG
Duplex Selection
Collision Test
Reserved
DESCRIPTION
1 = PHY reset
0 = Normal operation
1 = Loopback mode active
0 = Normal operation
1 = 100 Mbps
0 = 10 Mbps
1 = Enable ANEG process
0 = Disable ANEG process
1 = Power down active
0 = Normal operation
1 = Isolation in process
0 = Normal operation
1 = Restart the ANEG process
0 = Normal operation
1= Full Duplex mode
0 = Half duplex mode
1 = Collision test active
0 = Normal operation
Write as 0; ignore on read
DEFAULT
0
0
1
1
0
0
0
1
0
TYPE
RW
SC
RW
RW
RW
RW
RW
RW
SC
RW
RW
SMSC DS – LAN83C180
Page 13
Rev. 08/24/2001
SMSC [ SMSC CORPORATION ]
