Reg 24 - LAN83C180 Specific Register
BIT
15:14
13
BIT NAME
Test Access
LED Control
DESCRIPTION
Reserved SMSC test access only
0 = COLST active on collision
1 = COLST active on Sync/polarity
0 = MINT output active low
DEFAULT TYPE
00b
R/W
0
R/W
12
MINT POL
0
R/W
1 = MINT output active high
11
10
Pol Dis
SQE Disable
Disable 10BASE-T autopolarity correction
0 = SQE generation (normal operation)
1 = No SQE generation
0
0
R/W
R/W
9
8
JAB Disable
Loop 10
0 = In case of jabber the 10BASE-T will cut the
frame (normal operation)
1 = Jabber function disable
Disable loopback of TX to RX in 10BASE-T half
duplex
0
0
R/W
R/W
7
6
5
Force RX
Force TX
CRS_CTL
Force reception regardless of link
Force transmission regardless of link
CRS behavior in FDX –
0
0
0
R/W
R/W
R/W
0 = CRS is active during transmission only
1= CRS active during reception only
0 = Normal operation
1 = Disable the MD preamble function
0 = Normal operation
1 = Bypass the aligner function
0 = Normal operation
1 = Bypass the 4B5B encoder function
0 = Normal operation
1 = Bypass the 4B5B scrambler function
Disconnect mechanism enable
4
3
2
1
0
MF
0
0
0
0
R/W
R/W
R/W
R/W
Byp ALIGN
Byp ENC
Byp SCR
DISCEN
0 – DTE
1 – RPT
Reg 25 - ANEG Status
BIT
15
14
13
12:8
7
BIT NAME
DESCRIPTION
Test mode only - do not set high
Test mode only - do not set high
10BASE-T polarity sense
PHY address
DEFAULT
TYPE
R/W
R/W
RO
RO
RO
Reserved
Reserved
Pol
0
0
0
PA<4:0>
0
PA
Aneg complete 0 = Aneg completed
1 = Aneg did not complete (same as 1.5)
6
5
Duplex
ANEG result - duplex operation
0 = HDX, 1 = FDX
ANEG result - speed of operation
0 = 10, 1 = 100
0
0
RO
RO
Speed
4
0:3
Ability mtc
ANEG state
1 = abilities matched
ANEG state machine current state
0
0
RO
RO
Reg 26 - Symbol Error Counter
BIT
15:0
BIT NAME
RX_ERR
counter
DESCRIPTION
Number of RX_ERR events since last read –
clears either in change of speed or read of this
reg.
DEFAULT TYPE
0
RO
SC
SMSC DS – LAN83C180
Page 16
Rev. 08/24/2001
SMSC [ SMSC CORPORATION ]
