High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
5.1
SMI Register Mapping
The following registers are supported (register numbers are in decimal):
Table 5.33 SMI Register Mapping
REGISTER #
DESCRIPTION
Basic Control Register
GROUP
0
Basic
1
Basic Status Register
Basic
2
PHY Identifier 1
Extended
Extended
Extended
Extended
Extended
3
PHY Identifier 2
4
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Silicon Revision Register
5
6
16
17
18
20
21
22
23
27
28
29
30
31
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Mode Control/Status Register
Special Modes
TSTCNTL – Testability/Configuration Control
TSTREAD1 – Testability data Read for LSB
TSTREAD2 – Testability data Read for MSB
TSTWRITE – Testability/Configuration data Write
Control / Status Indication Register
Special internal testability controls
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
5.2
SMI Register Format
The mode key is as follows:
■
RW = read/write,
■
■
■
■
■
■
SC = self clearing,
WO = write only,
RO = read only,
LH = latch high, clear on read of register,
LL = latch low, clear on read of register,
NASR = Not Affected by Software Reset
Rev. 0.8 (11-16-04)
SMSC LAN83C185
DATA3S4HEET
SMSC [ SMSC CORPORATION ]
