Non-PCI Single-Chip Full Duplex Ethernet Controller
LAN91C96I Datasheet Revision History
PAGE(S)
2
2
86
59
71
10
11
42
109, 110
SECTION/FIGURE/ENTRY
Ordering Information
Ordering Information
11.2 DC Electrical Characteristics
Chapter 8 Theory of Operation
8.6 Power Down
Figure 3.1 – Pin Configuration of
LAN91C96I QFP
Figure 3.2
−
Pin Configuration of
LAN91C96I TQFP
I/O Space – Bank1 Offset 2
Figure 13.1 - 100 Pin QFP Package,
Figure 13.2 - 100 Pin TQFP
Package
Chapter 4 - Description of Pin
Functions
IO Space Bank 2 Offset 2 – Interrupt
Figure 7.2 – Interrupt Structure
Bank 3 Offset A – Revision Register
8.1, 8.2 Typical Flow of Events for
Transmit
Title and document
Figure 8.1 – Interrupt Service
Routine
Figure 6.1 – Data Packet Format
Data area in ram
Figure 5.4 – LAN91C96i Internal
Block Diagram with Data Path
DC Electrical Characteristics
Figure 8.4 – TXEMPTY INTR
CORRECTION
Lead-free ordering information modified
Added lead-free ordering information
Modified Supply Current to power down
mode current
Modified descriptions of “Magic
Packet
Support”
Modified description of under heading.
Modified pin number 95
(removed nPCMCIA)
Modified pin number 93
(removed nPCMCIA)
Modified I/O base address 300h decoding
New pin package diagrams
DATE
REVISED
11/18/04
09/10/04
12/18/03
12/18/03
12/18/03
10/31/03
10/31/03
10/07/02
09/18/02
15
50
55
59
61
1
64
30
30
25
86
67
Add description of RBIAS pin
Modified description of Interrupt Registers
Modified Interrupt Structure Figure
Changed the REV ID to 9
Modified Flow Chart
Non-PCI replaces ISA in title. Local Bus
replaces ISA throughout document.
Figure has been updated.
Changed Max Offset To 1534 From 1536
Number of Bytes in Data Area Changed to
1531 from 2034
Modify figure
Update 3.3V Characteristics numbers to
replace TBD
Updated figure
08/01/02
08/01/02
08/01/02
08/01/02
08/01/02
04/15/02
04/15/02
07/26/01
07/26/01
07/26/01
07/26/01
03/21/01
SMSC DS – LAN91C96I
Page 3
Rev. 11/18/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
