Non-PCI Single-Chip Full Duplex Ethernet Controller
Table of Contents
Chapter 1
Chapter 2
Chapter 3
3.1
4.1
5.1
5.2
5.3
5.4
General Description ............................................................................................................. 6
Overview ............................................................................................................................... 7
Pin Configurations ............................................................................................................. 10
Description of Pin Functions ............................................................................................. 15
Functional Description....................................................................................................... 20
Local Bus vs. Pin Requirements ....................................................................................................... 13
Buffer Symbols .................................................................................................................................. 18
Buffer Memory ................................................................................................................................... 21
Interrupt Structure ............................................................................................................................. 27
Reset Logic........................................................................................................................................ 28
Power Down Logic States ................................................................................................................. 28
Chapter 4
Chapter 5
Chapter 6
Chapter 7
7.1
7.2
7.2.1
Packet Format in Buffer memory for Ethernet............................................................... 30
Registers Map in I/O Space............................................................................................... 33
Bank Select Register ..............................................................................................................................35
I/O Space Access.............................................................................................................................. 34
I/O Space Registers Description ....................................................................................................... 35
Chapter 8
8.1
8.2
8.3
8.4
8.5
8.6
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
10.1
10.2
11.1
11.2
Theory of Operation .......................................................................................................... 59
Typical Flow Of Events For Transmit (Auto Release =0).................................................................. 61
Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 62
Typical Flow Of Events For Receive ................................................................................................. 63
Memory Partitioning .......................................................................................................................... 69
Interrupt Generation .......................................................................................................................... 69
Power Down ...................................................................................................................................... 71
Chapter 9
Functional Description of the Blocks................................................................................ 73
Memory Management Unit ................................................................................................................ 73
Arbiter ................................................................................................................................................ 73
Bus Interface ..................................................................................................................................... 74
Wait State Policy ............................................................................................................................... 74
Arbitration Considerations ................................................................................................................. 75
DMA Block......................................................................................................................................... 75
Packet Number FIFOs....................................................................................................................... 76
CSMA Block ...................................................................................................................................... 77
Network Interface .............................................................................................................................. 79
10BASE-T ...................................................................................................................................... 79
AUI ................................................................................................................................................. 79
Physical Interface........................................................................................................................... 80
Transmit Functions......................................................................................................................... 80
Transmit Drivers............................................................................................................................. 80
Receive Functions.......................................................................................................................... 80
Chapter 10
Board Setup Information ............................................................................................... 82
Diagnostic LEDs............................................................................................................................. 83
Bus Clock Considerations.............................................................................................................. 83
Chapter 11
Operation Description .................................................................................................... 85
Maximum Guaranteed Ratings*..................................................................................................... 85
DC Electrical Characteristics ......................................................................................................... 86
Chapter 12
Rev. 11/18/2004
Timing Diagrams ............................................................................................................ 92
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