Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
30:28
EEPROM Controller Command (EPC_COMMAND)
R/W
000b
This field is used to issue commands to the EEPROM controller. The
EEPROM controller will execute a command when the EPC_BUSY bit is set.
A new command must not be issued until the previous command completes.
The field is encoded as follows:
[30]
0
[29]
0
[28]
0
Operation
READ
0
0
1
RESERVED
RESERVED
WRITE
0
1
0
0
1
1
1
0
0
RESERVED
RESERVED
RESERVED
RELOAD
1
0
1
1
1
0
1
1
1
2
Note:
Only the READ, WRITE and RELOAD commands are valid for I C
mode. If an unsupported command is attempted, the EPC_BUSY
bit will be cleared and EPC_TIMEOUT will be set.
The EEPROM operations are defined as follows:
READ (Read Location)
This command will cause a read of the EEPROM location pointed to by the
EPC_ADDRESS bit field. The result of the read is available in the EEPROM
Data Register (E2P_DATA).
WRITE (Write Location)
If erase/write operations are enabled in the EEPROM, this command will
cause the contents of the EEPROM Data Register (E2P_DATA) to be written
to the EEPROM location selected by the EPC_ADDRESS field.
RELOAD (EEPROM Loader Reload)
Instructs the EEPROM Loader to reload the device from the EEPROM. If a
value of A5h is not found in the first address of the EEPROM, the EEPROM
is assumed to be un-programmed and the RELOAD operation will fail. The
CFG_LOADED bit indicates a successful load. Following this command, the
device will enter the not ready state. The Device Ready (READY) bit in the
Hardware Configuration Register (HW_CFG) should be polled to determine
when the RELOAD is complete.
27:19
18
RESERVED
RO
RO
-
EEPROM Loader Address Overflow (LOADER_OVERFLOW)
This bit indicates that the EEPROM Loader tried to read past the end of the
EEPROM address space. This indicates misconfigured EEPROM data.
0b
This bit is cleared when the EEPROM Loader is restarted with a RELOAD
command, or a Digital Reset (DIGITAL_RST).
17
EEPROM Controller Timeout (EPC_TIMEOUT)
R/WC
0b
This bit is set when a timeout occurs, indicating the last operation was
unsuccessful. If an EEPROM WRITE operation is performed, and no
response is received from the EEPROM within 30mS, the EEPROM
controller will timeout and return to its idle state.
The bit is also set if the EEPROM fails to respond with the appropriate
ACKs, if the EEPROM slave device holds the clock low for more than 30mS,
2
if the I C bus is not acquired within 1.92 seconds, or if an unsupported
EPC_COMMAND is attempted.
This bit is cleared when written high.
SMSC LAN9303/LAN9303i
149
Revision 1.3 (08-27-09)
DATASHEET
SMSC [ SMSC CORPORATION ]
