USB 2.0 to 10/100 Ethernet Controller
Datasheet
Table 3.1 MII Interface Pins (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Management
Data
MDIO
IS/O8
(PD)
In external PHY mode, this pin provides the
management data to/from the external PHY.
(External
PHY Mode)
General
GPIO1
IS/O8/
OD8
(PU)
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Purpose I/O 1
(Internal PHY
Mode Only)
1
Note:
(LAN9500A/LAN9500Ai only)
This pin may serve as the
PME_MODE_SEL input when Internal
PHY and PME modes of operation are
in effect. Refer to Chapter 6, "PME
Operation," on page 41 for additional
information.
Management
Clock
(External
PHY Mode)
MDC
GPIO2
TXD3
O8
(PD)
In external PHY mode, this pin outputs the
management clock to the external PHY.
1
General
IS/O8/
OD8
(PU)
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Purpose I/O 2
(Internal PHY
Mode Only)
TransmitData
3
O8
(PU)
In external PHY mode, this pin functions as the
transmit data 3 output to the external PHY.
(External
PHY Mode)
General
GPIO7
IS/O8/
OD8
(PU)
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Purpose I/O 7
(Internal PHY
Mode Only)
Note:
(LAN9500A/LAN9500Ai ONLY):
GPIO7 may provide additional PHY Link
Up related functionality.
EEPROM
Size
EEP_SIZE
IS
(PU)
The EEP_SIZE strap selects the size of the
EEPROM attached to the device.
1
Configuration
Strap
0 = 128 byte EEPROM is attached and a total of
seven address bits are used.
1 = 256/512 byte EEPROM is attached and a
total of nine address bits are used.
Note:
A 3-wire style 1K/2K/4K EEPROM that
is organized for 128 x 8-bit or 256/512 x
8-bit operation must be used.
See Note 3.1 for more information on
configuration straps.
Revision 1.1 (04-18-13)
SMSC LAN950x Family
DATA1S4HEET
SMSC [ SMSC CORPORATION ]
