USB 2.0 to 10/100 Ethernet Controller
Datasheet
Table 3.6 Ethernet PHY Pins (continued)
BUFFER
TYPE
O8
NUM PINS
NAME
PHY Interrupt
(Internal PHY
Mode)
SYMBOL
nPHY_INT
DESCRIPTION
In internal PHY mode, this pin can be configured
to output the internal PHY interrupt signal.
Note:
The internal PHY interrupt signal is
active-high.
1
PHY Interrupt
(External
PHY Mode)
+3.3V Analog
Power Supply
4
nPHY_INT
IS
(PU)
P
In external PHY mode, the active-low signal on
this pin is input from the external PHY and
indicates a PHY interrupt has occurred.
Refer to the device reference schematic for
connection information.
Note:
Pin 7 is a no-connect (NC) for
LAN9500A/LAN9500Ai, but may be
connected to VDD33A for backward
compatibility with LAN9500/LAN9500i.
VDD33A
External PHY
Bias Resistor
1
EXRES
AI
Used for the internal bias circuits. Connect to an
external resistor to ground.
For LAN9500A/LAN9500Ai use 12.0K, 1%.
For LAN9500/LAN9500i use 12.4K, 1%.
Ethernet PLL
Power Supply
1
VDDPLL
P
This pin must be connected to VDDCORE for
proper operation.
Refer to
and the device reference schematic for
additional connection information.
Table 3.7 I/O Power Pins, Core Power Pins, and Ground Pad
BUFFER
TYPE
P
P
NUM PINS
5
NAME
+3.3V I/O
Power
Digital Core
Power Supply
Output
Ground
SYMBOL
VDD33IO
VDDCORE
DESCRIPTION
Refer to the device reference schematic for
connection information.
Refer to
and the device reference schematic for
connection information.
Common Ground
2
Exposed
pad on
package
bottom
VSS
P
Revision 1.1 (04-18-13)
DATASHEET
22
SMSC LAN950x Family
SMSC [ SMSC CORPORATION ]
