PIN DESCRIPTION
I/O
12t
I/O
12ts
OUT
12
AOUT
OD
12
IN
t
IN
ts
AIN
- TTL level bi-directional pin with 12 mA source-sink capability
- TTL level and schmitt trigger
- Output pin with 12 mA source-sink capability
- Output pin (Analog)
- Open-drain output pin with 12 mA sink capability
- TTL level input pin
- TTL level input pin and schmitt trigger
- Input pin (Analog)
DESCRIPTION OF PIN FUNCTIONS
PIN NAME
nIOR
nIOW
CLKIN
D7~D2
PIN NO.
1
2
3
4-9
TYPE
IN
t s
IN
t s
IN
t
I/O
12t
DESCRIPTION
An active low standard ISA bus I/O Read
Control.
An active low standard ISA bus I/O Write
Control.
System clock input. Can select 48MHz or 24MHz
or 14.318MHz. The default is 24MHz.
Bi-directional ISA bus Data lines. D0
corresponds to the low order bit, with D7 the
high order bit. These pins are activated if pin
ADRMSEL=0.
Bi-directional ISA bus Data lines. This pin is
activated if pin ADRMSEL=0. /Fan speed control
PWM output. This pin is activated if pin
ADRMSEL=1.
Bi-directional ISA bus Data lines. This pin is
activated if pin ADRMSEL=0. /Fan speed control
PWM output. This pin is activated if pin
ADRMSEL=1.
Voltage Supply readouts from P6. This value is
read in the VID/Fan Divisor Register.
+5V V
CC
power. Bypass with the parallel
combination of 10&F (electrolytic or tantalum)
and 0.1&F (ceramic) bypass capacitors.
Internally connected to all digital circuitry.
Master reset input.
CASE OPEN detection. An active low input from
an external device when the case is opened.
This signal can be latched if VBAT is connect to
a battery, even if the MON35W42 is power off.
Voltage Supply readouts from P6. This value is
read in the bit <0> of Device ID Register.
0V to +5V amplitude fan tachometer input. /
Fan speed control PWM output.
6
D1/
PWMOUT4
D0/
PWMOUT3
VID1
V
CC
(+5V)
10
I/O
12t
OUT
12t
11
I/O
12t
OUT
12t
12
13
IN
t
POWER
GNDD
MR
nCASEOPEN
14
15
16
DGROUND
IN
t s
IN
t
VID4
FAN3IO/
PWMOUT2
17
18
IN
t
I/O
12t
SMSC [ SMSC CORPORATION ]
