FUNCTIONAL DESCRIPTION
General Description
The MON35W42 provides 7 analog positive
inputs, 3 fan speed monitors, up to 4 sets of fan
PWM (Pulse Width Modulation) control, 3
thermal inputs from remote thermistors or
®
2N3904 transistors or Pentium II (Deschutes)
thermal diode outputs, case open detection and
beep function output. When the monitored value
exceed the set limit value for voltage,
temperature, or fan counter, the beep output can
be generated. Once the monitor function on the
chip is enabled, the watch dog machine monitors
each function and stores the values. If the
monitored value exceeds the limit value, the
interrupt status is set to 1and an interrupt can be
generated.
Access Interface
The MON35W42 provides two interfaces for the
microprocessor to read/write internal registers.
ISA interface
The ISA Bus can be used to access the internal
registers of the MON35W42. This uses an Index
register and Data register to access the internal
registers. The upper address bits of the ISA bus
(bits15:3) must be externally decoded for the
Chip Select (nCS), the recommended address is
290h-297h. The Chip then uses the lower three
ISA address bits (bits 2:0) to decode the Index
and Data Registers. These two I/O registers are
described as following:
Port 295h: Index register.
Port 296h: Data register
The register structure is shown in Figure 1.
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