CXA3197R
Pin Description and I/O Pin Equivalent Circuit
Pin No.
Symbol
I/O Typical voltage level
Equivalent circuit
Description
1 to 6
45 to 48
DA0 to DA9
I
TTL
1
DV
CC
1
Side A data input.
to 6
45 to 48
7
to 16
DGND1
1.5V
7 to 16
DB0 to DB9
I
TTL
Side B data input.
DV
CC
1
17
DIV2IN
I
TTL
17
1.5V
DGND1
1/2 frequency-divided
clock input.
Use this pin in MUX.1A
or MUX.2 mode.
Leave open for other
modes.
DV
CC
1
18
DIV2OUT
O
TTL
100K
18
DGND1
1/2 frequency-divided
clock output.
The 1/2 frequency-
divided clock signal
(DIV2OUT) is output in
MUX.1A mode.
Set to high impedance
for other modes.
DV
CC
1
19
CLK/T
I
TTL
19
1.5V
DGND1
Clock input.
Use this pin when the
clock is input at TTL
level.
At this time, leave Pins
20 and 21 open.
–5–
SONY [ SONY CORPORATION ]
