CXA3197R
Pin No.
Symbol
I/O Typical voltage level
Equivalent circuit
Description
Clock input.
Use this pin when the
clock is input at PECL
level.
At this time, leave
Pin 19 open.
CLKP/E and CLKN/E
are complementary and
should be used together.
CLKP/E complementary
input.
Reset signal input.
When multiple
CXA3197R are
operated at the same
time in MUX.1A or
MUX.1B mode, the start
timing of the internal 1/2
frequency divider
circuits should be
matched.
At this time, the reset
signal is used; when the
reset signal is at TTL
level, Pin 22 is used and
Pins 23 and 24 are left
open. When the reset
signal is at PECL level,
Pins 23 and 24 are used
and Pin 22 is left open.
The reset signal polarity
can be set by Pin 39
(R POLARITY).
Leave the reset pin
open when other modes
are used.
RESETP/E and
RESETN/E are
complementary and
should be used together.
DV
CC
1
20
CLKP/E
I
PECL
20
21
DGND1
21
CLKN/E
I
PECL
DV
CC
1
22
RESET/T
I
TTL
22
1.5V
DGND1
23
RESETP/E
I
PECL
DV
CC
1
23
24
24
RESETN/E
I
PECL
DGND1
25
DGND2
Single power
supply: GND
Dual power
supply: –5V
I
TTL
DV
CC
1
Digital power supply.
26
C1
Function setting.
27
C2
I
TTL
26
27
28
1.5V
Function setting.
28
C3
I
TTL
DGND1
Function setting.
–6–
SONY [ SONY CORPORATION ]
