CXD2470R
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VDI
HDI
Enlarged view
VDI
HDI
0.2V
DDd
ts1
SEN
0.8V
DDd
th1
0.2V
DDd
∗
Be sure to maintain a constantly high SEN logic level near the falling edge of VDI.
(Within the recommended operating conditions)
Symbol
Definition
SEN setup time, activated by the falling edge of VDI
SEN hold time, activated by the falling edge of VDI
Min.
0
200
Typ.
Max.
Unit
ns
ns
t
s1
t
h1
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2470R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD2470R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8V
DDd
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
5
Typ.
Max.
100
Unit
ns
tpdPULSE Output signal delay, activated by the rising edge of SEN
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SONY [ SONY CORPORATION ]
