CXK581000ATM-70LL 参数 Datasheet PDF下载

CXK581000ATM/AYM/AM/AP

• Write cycle (2) :

CE1 control

t

WC

Address

t

AW

OE

t

AS

CE1

t

CW

CE2

t

WP

WE

t

DW

Data in

Data valid

t

DH

t

CW

t

WR1

(

∗

3)

Data out

High impedance

• Write cycle (3) :

CE2 control

t

WC

Address

t

AW

OE

t

CW

CE1

t

AS

CE2

t

WP

WE

t

DW

Data in

Data valid

t

DH

t

OW

CW

t

WR1

(

∗

3)

Data out

High impedance

∗

1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.

∗

2 Do not apply the data input voltage of the opposite phase to the output while the I/O pin is in output condition.

∗

3

t

WR1

is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until

the end of the write cycle.

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