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CXL1518M 参数 Datasheet PDF下载

CXL1518M图片预览
型号: CXL1518M
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , CCD信号处理器 [CMOS-CCD Signal Processor]
分类和应用:
文件页数/大小: 7 页 / 100 K
品牌: SONY [ SONY CORPORATION ]
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CXL1517M/1518M
Notes)
1) Linearity testing
For A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a
sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C
channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then
input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum
output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output
amplitude as Sout min. The linearity of the respective channels is defined as:
Lin. = Sout max – Sout min
×
200 [%]
Sout max + Sout min
2) Calculation of insertion gain difference
As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin,
the insertion gain difference between channels
∆G
as:
∆G
=
|
1 – 10
(
Gmax20 Gmin
)
| ×
100 [%]
3) Calculation of linearity difference
Define B channel linearity as L
B
and C channel linearily as L
C
we obtain the difference
∆L
BC
as:
∆L
BC
=
|
L
B
– L
C
|
[%]
4) Cross-talk calculation
CRTa
: The cross-talk value of A channel when B and C channels are input
: The output value of A channel when A channel is input
OUT
A
-
a
SW3-a, SW4-a, SW5, 6-b
OUT
A
-
bc
: The output value of A channel when B and C channels are input
(Cross-talk component)
SW3-a, SW4-b, SW5, 6-a
CRTa =
OUT
A
-
bc
OUT
A
-
a
×
100 [%]
Clock Waveform Timing
(140)
210ns
(52.5)
87.5ns
10ns
10ns
90%
XDL1
50%
10%
90%
50%
10%
17.5ns
10ns
(52.5)
87.5ns
10ns
90%
XDL2
50%
10%
90%
50%
10%
–5–
The value in brackets is for CXL1517M.