Block Diagram
TEX
TX
XTAL
V
DD
Vss
RST
SPC700
CPU CORE
CLOCK GENERATOR/
SYSTEM CONTROL
SEG0 to SEG31
32
PORT A
AN0 to AN7
8
A/D CONVERTER
INT0
INT1
INT2
NMI/INT3
2
EXTAL
8
PA0 to PA7
LCD
CONTROLLER/
DRIVER
ROM
8K/12K/16K BYTES
RAM
448 BYTES
PORT B
COM0 to COM3
4
8
PB0 to PB7
RMC
REMOCON
FIFO
PORT D
PWM0
PWM1
14BIT PWM GENERATOR
8BIT PWM GENERATOR
INTERRUPT CONTROLLER
V
L
V
LC1
V
LC2
V
LC3
PORT C
8
PC0 to PC7
PRESCALER/
TIME BASE TIMER
32kHz
TIMER/COUNTER
SERIAL
INTERFACE
UNIT 0
FIFO
PORT E
CS0
SI0
SO0
SCK0
CS1
SI1
SO1
SCK1
2
EC
8BIT TIMER/COUNTER 0
PORT F
CXP83408/83412/83416, CXP83409/83413/83417
ADJ
2
PORT H
–2–
8
PD0 to PD7
5
2
PE0 to PE4
PE5 to PE6
8
PF0 to PF7
TO
8BIT TIMER 1
1
PH0
SONY [ SONY CORPORATION ]
