ICX229AK
Block Diagram and Pin Configuration
V
OUT
GND
Vφ
3
Vφ
1
Vφ
2
NC
Vφ
4
1
Note)
(Top View)
7
6
5
4
3
2
Cy
Ye
G
Ye
Mg
Ye
G
Cy
Mg
Cy
G
Cy
Mg
Ye
G
Ye
Mg
Ye
G
Vertical Register
Mg
Cy
G
Cy
Mg
Horizontal Register
Note)
13
: Photo sensor
8
9
10
11
12
14
GND
V
DD
RG
V
L
Pin Description
Pin No.
1
2
3
4
5
6
7
Symbol
Vφ
4
Vφ
3
Vφ
2
Vφ
1
NC
GND
V
OUT
GND
Signal output
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Pin No.
8
9
10
11
12
13
14
Symbol
V
DD
GND
φSUB
V
L
RG
Hφ
1
Hφ
2
Description
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Absolute Maximum Ratings
Item
V
DD
, V
OUT
, RG –
φSUB
Against
φSUB
Vφ
1
, Vφ
3
–
φSUB
Vφ
2
, Vφ
4
, V
L
–
φSUB
Hφ
1
, Hφ
2
, GND –
φSUB
V
DD
, V
OUT
, RG – GND
Against GND
Vφ
1
, Vφ
2
, Vφ
3
, Vφ
4
– GND
Hφ
1
, Hφ
2
– GND
Against V
L
Vφ
1
, Vφ
3
– V
L
Vφ
2
, Vφ
4
, Hφ
1
, Hφ
2
, GND – V
L
Voltage difference between vertical clock input pins
Between input clock
pins
Storage temperature
Operating temperature
∗
1
+21V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
Hφ
1
– Hφ
2
Hφ
1
, Hφ
2
– Vφ
4
Ratings
–32 to +12
–40 to +15
–40 to +0.3
–32 to +0.3
–0.3 to +17
–7 to +14
–7 to +4.2
–0.3 to +21
–0.3 to +12
to +12
–5 to +5
–12 to +12
–30 to +80
–10 to +60
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗
1
Remarks
φSUB
Hφ
1
Hφ
2
SONY [ SONY CORPORATION ]
