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AM29DL324GT70EI 参数 Datasheet PDF下载

AM29DL324GT70EI图片预览
型号: AM29DL324GT70EI
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位( 4米×8位/ 2的M× 16位) CMOS 3.0伏只,同时操作闪存 [32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 58 页 / 1293 K
品牌: SPANSION [ SPANSION ]
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D A T A
Table 13.
Addresses
(Word Mode)
40h
41h
42h
43h
44h
45h
Addresses
(Byte Mode)
80h
82h
84h
86h
88h
8Ah
S H E E T
Primary Vendor-Specific Extended Query
Description
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
Data
0050h
0052h
0049h
0031h
0033h
0004h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
8Ch
8Eh
90h
92h
94h
96h
98h
9Ah
0002h
0001h
0001h
0004h
00XXh
0000h
0000h
0085h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank 2 (Uniform Bank)
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
4Eh
9Ch
0095h
4Fh
9Eh
000Xh
Note:
The number of sectors in Bank 2 is device dependent.
Am29DL322 = 38h, Am29DL323 = 30h, Am29DL324 = 20h
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 14 defines the valid register command
sequences.
Writing incorrect address and data values
or writing them in the improper sequence may place
the device in an unknown state.
A reset command is
then required to return the device to reading array
data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. After completing a programming operation
in the Erase Suspend mode, the system may once
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Am29DL32xG
25686B10 December 4, 2006